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? 2005-2014 microchip technology inc. ds20001936d-page 1 mcp1726 features: ? 1a output current capability ? input operating voltage range: 2.3v to 6.0v ? adjustable output voltage range: 0.8v to 5.0v ? standard fixed output voltages: - 0.8v, 1.2v, 1.8v, 2.5v, 3.0v, 3.3v, 5.0v ? low dropout voltage: 220 mv typical at 1a ? typical output voltage tolerance: 0.5% ? stable with 1.0 f ceramic output capacitor ? fast response to load transients ? low supply current: 140 a (typical) ? low shutdown supply current: 0.1 a (typical) ? adjustable delay on power good output ? short-circuit current limiting and overtemperature protection ? 3x3 dfn-8 and soic-8 package options applications: ? high-speed driver chipset power ? networking backplane cards ? notebook computers ? network interface cards ? palmtop computers ? 2.5v to 1.xv regulators description: the mcp1726 is a 1a low dropout (ldo) linear regulator that provides high current and low output voltages in a very small package. the mcp1726 comes in fixed or adjustable output voltage versions, with an output voltage range of 0.8v to 5.0v. the 1a output current capability and low output voltage capability make the mcp1726 a good choice for new sub-1.8v output voltage ldo applications that have high current demands. the mcp1726 is stable using ceramic output capacitors that inherently provide lower output noise and reduce the size and cost of the entire regulator solution. only 1 f of output capacitance is needed to stabilize the ldo. using cmos construction, the quiescent current consumed by the mcp1726 is typically less than 140 a over the entire input voltage range, making it attractive for portable computing applications that demand high output current. when the mcp1726 is shut down, the quiescent current is reduced to less than 0.1 a. the scaled-down output voltage is internally monitored and a power good (pwrgd) output is provided when the output is within 92% of regulation (typical). an external capacitor can be used on the c delay pin to adjust the delay from 1 ms to 300 ms. the overtemperature and short-circuit current limiting provide additional protection for the ldo during system fault conditions. package types shdn v in gnd adj c delay 1 2 3 4 pwrgd v out v in 8 7 6 5 mcp1726-adj soic shdn v in gnd v out c delay 1 2 3 4 pwrgd v out v in 8 7 6 5 mcp1726-xx soic shdn v in gnd adj c delay 1 2 3 4 8 7 6 5 pwrgd v out v in ep 9 mcp1726-adj 3x3 dfn shdn v in gnd v out c delay 1 2 3 4 8 7 6 5 pwrgd v out v in ep 9 mcp1726-xx 3x3 dfn 1a, low-voltage, low quiescent current ldo regulator
mcp1726 ds20001936d-page 2 ? 2005-2014 microchip technology inc. typical application mcp1726 adjustable output voltage 1 2 3 45 6 7 8 1f pwrgd v out =1.2v @ 1a 100 k ? 4.7 f v in = 2.3v to 2.8v on off 20 k ? 40 k ? r 1 r 2 c 1 c 2 r 3 1000 pf c 3 mcp1726 fixed output voltage v in shdn gnd pwrgd c delay v out v out 1 2 3 45 6 7 8 pwrgd v out =1.8v @ 1a v in = 2.3v to 2.8v on off v in 1f 100 k ? 4.7 f c 1 c 2 r 1 1000 pf c 3 v in shdn gnd pwrgd c delay adj v out v in
2005-2014 microchip technology inc. ds20001936d-page 3 mcp1726 functional block diagram ea + ? v out pmos r f c f i sns v ref comp 92% of v ref t delay pwrgd c delay v in gnd soft-start adj reference shdn shdn shdn undervoltage lockout (uvlo) overtemperature sensing driver w/ limit and shdn v in
mcp1726 ds20001936d-page 4 2005-2014 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? v in ....................................................................................6.5v maximum voltage on any pin .. (gnd ? 0.3v) to (v dd +0.3)v maximum junction temperature, t j ........................... +150c maximum power dissipation ......... internally-limited ( note 6 ) storage temperature.....................................-65c to +150c ? notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this sp ecification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc characteristics electrical specifications: unless otherwise noted, v in =(v r + 0.5v) or 2.3v, whichever is greater, i out =1ma, c in =c out = 4.7 f (x7r ceramic), t a =+25c. boldface type applies for junction temperatures, t j ( note 7 ), of -40c to +125c . parameters sym. min. typ. max. units conditions input operating voltage v in 2.3 6.0 v note 1 input quiescent current i q ? 140 220 a i l =0ma, v in =v r +0.5v, v out = 0.8v to 5.0v input quiescent current for shdn mode i shdn ?0.1 3 a shdn =gnd maximum output current i out 1 ??av in = 2.3v to 6.0v ( note 1 ) line regulation ' v out / (v out x ' v in ) ?0.05 0.3 %/v (v r +0.5)v d v in d 6v load regulation ' v out /v out -1.5 0.5 1.5 %i out = 1 ma to 1a, v in =(v r + 0.6)v ( note 4 ) output short-circuit current i out_sc ?1.7? av in =(v r + 0.5)v, r load <0.1 : , peak current adjust pin characteristics adjust pin reference voltage v adj 0.402 0.410 0.418 vv in = 2.3v to v in =6.0v, i out =1ma adjust pin leakage current i adj -10 0.01 +10 na v in =6.0v, v adj =0vto6v adjust temperature coefficient tcv out ? 40 ? ppm/c note 3 fixed-output characteristics voltage regulation v out v r ?2.5% v r 0.5% v r +2.5% v note 2 dropout characteristics dropout voltage v in ?v out ? 220 500 mv i out =1a, v in(min) =2.3v ( note 5 ) note 1: the minimum v in must meet two conditions: v in t 2.3v and v in t v r +2.5% v dropout . 2: v r is the nominal regulator output voltage for the fixed cases. v r = 1.2v, 1.8v, etc. v r is the desired set point output voltage for the adjustable cases. v r =v adj x((r 1 /r 2 ) + 1). see figure 4-1 . 3: tcv out =(v out-high ?v out-low )x10 6 /(v r x ' temperature). v out-high is the highest voltage measured over the temperature range. v out-low is the lowest voltage meas ured over the temperature range. 4: load regulation is measured at a constant junction temperature using low duty-c ycle pulse testing. load regulation is tested over a load range from 1 ma to the maximum specified output current. 5: dropout voltage is defined as the input-to-output voltage diff erential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of v in =v r +0.5v. 6: the maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., t a , t j , t ja ). exceeding the maximum allowable power dissipation will cause the device operati ng junction temperature to exceed the maximum 150c rating. sustained junction temperatures above 125c can impact device reliability. 7: the junction temperature is approximated by soaking the dev ice under test at an ambient temperature equal to the desired junction temperature. the test ti me is small enough such that the rise in the junction temperature over the ambient temperature is not significant.
? 2005-2014 microchip technology inc. ds20001936d-page 5 mcp1726 power good characteristics input voltage operating range for valid pwrgd v pwrgd_vin 1.0 ? 6.0 v t a = +25c 1.2 ? 6.0 t a = -40c to +125c i sink = 100 a pwrgd threshold voltage (referenced to v out ) pwrgd_thf 88 92 96 %v out < 2.5v, falling edge 89 92 95 %v out > 2.5v, falling edge pwrgd_thr 89 94 98 %v out < 2.5v, rising edge 90 93 96 %v out > 2.5v, rising edge pwrgd output voltage low v pwrgd_l ?0.2 0.4 vi pwrgd sink =1.2ma pwrgd leakage p wrgd_lk ?0.1?av pwrgd =v in =6.0v pwrgd time delay t pg ? 200 ? s c delay =open 10 30 55 ms c delay =0.01f ? 300 ? ms c delay =0.1f detect threshold to pwrgd active time delay t vdet-pwrgd ? 170 ? s shutdown input logic-high input v shdn-high 45 ??%v in v in = 2.3v to 6.0v logic-low input v shdn-low ?? 15 %v in v in = 2.3v to 6.0v shdn input leakage current shdn ilk -0.1 0.001 +0.1 a v in = 6v, shdn =v in , shdn =gnd ac performance output delay from shdn t or 100 s shdn = gnd to v in v out = gnd to 95% v r output noise e n ?2.0?v/ ? hz i out =200ma, f=1khz, c out = 1 f (x7r ceramic), v out =2.5v power supply ripple rejection ratio psrr ? 54 ? db f = 100 hz, c out =10f, i out =100ma, v inac =30mv pk-pk, c in =0f thermal shutdown temperature t sd ? 150 ? c i out =100a, v out =1.8v, v in =2.8v thermal shutdown hysteresis ? t sd ?10?ci out =100a, v out =1.8v, v in =2.8v dc characteristics (continued) electrical specifications: unless otherwise noted, v in =(v r + 0.5v) or 2.3v, whichever is greater, i out =1ma, c in =c out = 4.7 f (x7r ceramic), t a =+25c. boldface type applies for junction temperatures, t j ( note 7 ), of -40c to +125c . parameters sym. min. typ. max. units conditions note 1: the minimum v in must meet two conditions: v in ? 2.3v and v in ?? v r +2.5% ??? v dropout . 2: v r is the nominal regulator output voltage for the fixed cases. v r = 1.2v, 1.8v, etc. v r is the desired set point output voltage for the adjustable cases. v r =v adj x((r 1 /r 2 ) + 1). see figure 4-1 . 3: tcv out =(v out-high ?v out-low )x10 6 /(v r x ? temperature). v out-high is the highest voltage measured over the temperature range. v out-low is the lowest voltage meas ured over the temperature range. 4: load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. load regulation is tested over a load range from 1 ma to the maximum specified output current. 5: dropout voltage is defined as the input-to-output voltage diff erential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of v in =v r +0.5v. 6: the maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., t a , t j , ? ja ). exceeding the maximum allowable power dissipation will cause the device operati ng junction temperature to exceed the maximum 150c rating. sustained junction temperatures above 125c can impact device reliability. 7: the junction temperature is approximated by soaking the dev ice under test at an ambient temperature equal to the desired junction temperature. the test ti me is small enough such that the rise in the junction temperature over the ambient temperature is not significant.
mcp1726 ds20001936d-page 6 ? 2005-2014 microchip technology inc. temperature specifications electrical specifications: unless otherwise indicated, all limits apply for v in = 2.3v to 6.0v. parameters sym. min. typ. max. units conditions temperature ranges operating junction temperature range t j -40 ? +125 c steady state maximum junction temperature t j ? ? +150 c transient storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 8l 3x3 dfn ? ja ? 64 ? c/w 4-layer jc51-5 standard board with vias ? jc ?12? thermal resistance, 8l soic ? ja ? 163 ? c/w 4-layer jc51-7 standard board ? jc ?42?
? 2005-2014 microchip technology inc. ds20001936d-page 7 mcp1726 2.0 typical performance curves note: unless otherwise indicated, v in =v out + 0.5v, i out = 1 ma and t a =+25c. figure 2-1: quiescent current vs. input voltage (1.2v adjustable). figure 2-2: ground current vs. load current (1.2v adjustable). figure 2-3: quiescent current vs. junction temperature (1.2v adjustable). figure 2-4: line regulation vs. temperature (1.2v adjustable). figure 2-5: load regulation vs. temperature. figure 2-6: adjust pin voltage vs. temperature. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 100 110 120 130 140 150 160 170 180 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8 input voltage (v) quiescent current (a) -40oc +125c +25c v r = 1.2v (adj.) i out = 0 ma 120 140 160 180 200 220 240 260 280 300 0 200 400 600 800 1000 load current (ma) ground current (a) v in = 2.5v v in = 3.3v v r = 1.2v (adj.) 100 110 120 130 140 150 160 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) quiescent current (a) v in = 2.5v v in = 5.0v v in = 3.3v v r = 1.2v (adj.) i out = 0 ma -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) line regulation (%/v) i out = 1a i out = 500 ma i out = 100 ma i out = 1 ma v r = 1.2v (adj.) v in = 2.3v to 6.0 v 0.10 0.20 0.30 0.40 0.50 0.60 0.70 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) load regulation (%) v r = 0.8v v r = 1.8v v r = 3.3v v r = 5.0v v in = v r + 0.6v (or 2.3v) i out = 1 ma to 1a 408.50 409.00 409.50 410.00 410.50 411.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) adjust pin voltage (mv) v in = 6.0v v in = 2.3v i out = 1 ma
mcp1726 ds20001936d-page 8 ? 2005-2014 microchip technology inc. note: unless otherwise indicated, v in =v out + 0.5v, i out = 1 ma and t a =+25c. figure 2-7: dropout voltage vs. output current (adjustable version). figure 2-8: dropout voltage vs. temperature (adjustable version). figure 2-9: power good (pwrgd) time delay vs. temperature. figure 2-10: quiescent current vs. input voltage (0.8v fixed). figure 2-11: quiescent current vs. input voltage (3.3v fixed). figure 2-12: ground current vs. load current. 0 25 50 75 100 125 150 175 200 225 250 0 200 400 600 800 1000 output current (ma) dropout voltage (mv) v out = 5.0v v out = 2.5v adjustable version 190 200 210 220 230 240 250 260 270 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) dropout voltage (mv) v out = 5.0v v out =2.5v v out = 3.3v adjustable version i out = 1a 20 22 24 26 28 30 32 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) power good time delay (ms) v in =2.3v v in =5.5v v in =3.0v c delay = 10 nf 100 110 120 130 140 150 160 170 180 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 5.6 5.9 input voltage (v) quiescent current (a) +25c -40c +125c +90c v out = 0.8v i out = 0 ma 0 100 200 300 400 500 600 700 800 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 5.6 5.9 input voltage (v) quiescent current (a) +125c +25c -40c v out =3.3v i out = 0 ma 120 140 160 180 200 220 240 260 280 300 320 340 0 200 400 600 800 1000 load current (ma) ground current (a) v out =3.3v v out =0.8v v in = 2.3v for 0.8v device
2005-2014 microchip technology inc. ds20001936d-page 9 mcp1726 note: unless otherwise indicated, v in =v out + 0.5v, i out = 1 ma and t a =+25c. figure 2-13: quiescent current vs. temperature. figure 2-14: i shdn vs. temperature. figure 2-15: line regulation vs. temperature (0.8v fixed). figure 2-16: line regulation vs. temperature (3.3v fixed). figure 2-17: load regulation vs. temperature (v out < 2.5v fixed). figure 2-18: load regulation vs. temperature (v out t 2.5v fixed). 100 110 120 130 140 150 160 170 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) quiescent current (a) v out =0.8v v out =3.3v i out = 0 ma v in = 2.3v for 0.8v device 0 10 20 30 40 50 60 70 80 90 100 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) i shdn (na) v in =6.0v v in =3.3v v in =2.3v -0.025 -0.02 -0.015 -0.01 -0.005 0 0.005 0.01 0.015 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) line regulation (%/v) i out =1.0a i out =500 ma i out =100 ma i out =10 ma v out = 0.8v -0.01 -0.005 0 0.005 0.01 0.015 0.02 0.025 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) line regulation (%/v) i out =500 ma i out =1 ma i out =1a i out =100 ma v out = 3.3v 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) load regulation (%) v out =1.2v v out =0.8v v out =1.8v i out = 1 ma to 1000 ma v in = 2.3v -0.70 -0.65 -0.60 -0.55 -0.50 -0.45 -0.40 -0.35 -0.30 -0.25 -0.20 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) load regulation (%) v out =5.0v v out =3.3v v out =2.5v i out = 1 ma to 1000 ma v in = v out + 0.6v
mcp1726 ds20001936d-page 10 ? 2005-2014 microchip technology inc. note: unless otherwise indicated, v in =v out + 0.5v, i out = 1 ma and t a =+25c. figure 2-19: dropout voltage vs. load current. figure 2-20: dropout voltage vs. temperature. figure 2-21: short-circuit current vs. input voltage. figure 2-22: output noise voltage density vs. frequency. figure 2-23: power supply ripple rejection (psrr) vs. frequency (v out =1.2v adjustable). figure 2-24: power supply ripple rejection (psrr) vs. frequency (v out =1.2v adjustable). 0 25 50 75 100 125 150 175 200 225 250 0 200 400 600 800 1000 load current (ma) dropout voltage (mv) v out =5.0v v out =2.5v 180 190 200 210 220 230 240 250 260 270 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) dropout voltage (mv) v out =5.0v v out =2.5v v out =3.3v i out = 1a 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2.32.62.93.23.53.84.14.44.75.05.35.65.9 input voltage (v) short circuit current (a) v out =1.2v (fixed) 0.01 0.1 1 10 0.01 0.1 1 10 100 1000 frequency (khz) noise (v ? hz) v out =2.5v (adj) i out = 200 ma v out =0.8v (fixed) i out = 100 ma c out =1 f c in = 10 f 0 10 20 30 40 50 60 70 80 0.01 0.1 1 10 100 1000 frequency (khz) psrr (db) c out =10 f c in = 0 f i out = 100 ma v out = 1.2v v in = 2.5v 0 10 20 30 40 50 60 70 80 90 0.01 0.1 1 10 100 1000 frequency (khz) psrr (db) c out =22 f c in = 0 f i out = 100 ma v out = 1.2v v in = 2.5v
? 2005-2014 microchip technology inc. ds20001936d-page 11 mcp1726 note: unless otherwise indicated, v in =v out + 0.5v, i out = 1 ma and t a =+25c. figure 2-25: power supply ripple rejection (psrr) vs. frequency (v out =2.5v fixed). figure 2-26: power supply ripple rejection (psrr) vs. frequency (v out =2.5v fixed). figure 2-27: 2.5v (adjustable) start-up from v in . figure 2-28: 2.5v (adjustable) start-up from shutdown. figure 2-29: power good (pwrgd) timing with c bypass of 1000 pf. figure 2-30: power good (pwrgd) timing with c bypass of 0.01 f. 0 10 20 30 40 50 60 70 80 0.01 0.1 1 10 100 1000 frequency (khz) psrr (db) c out =10 f c in = 0 f i out = 100 ma v out = 2.5v v in = 3.3v 0 10 20 30 40 50 60 70 80 0.01 0.1 1 10 100 1000 frequency (khz) psrr (db) c out =22 f c in = 0 f i out = 100 ma v out = 2.5v v in = 3.3v v out v in pwrgd v out shdn pwrgd v out pwrgd v in v out v in pwrgd
mcp1726 ds20001936d-page 12 ? 2005-2014 microchip technology inc. note: unless otherwise indicated, v in =v out + 0.5v, i out = 1 ma and t a =+25c. figure 2-31: dynamic line response (1.2v fixed). figure 2-32: dynamic line response (2.5v fixed). figure 2-33: dynamic load response (2.5v fixed, 10 ma to 1000 ma). figure 2-34: dynamic load response (2.5v fixed, 100 ma to 1000 ma). v out v in c in = 1 f c out = 10 f i out = 100 ma 3.3v 2.3v v out v in c in = 1 f c out = 10 f i out = 100 ma 4.5v 3.5v v out v in c in = 47 f c out = 10 f i out v out v in c in = 47 f c out = 10 f i out
? 2005-2014 microchip technology inc. ds20001936d-page 13 mcp1726 3.0 pin description the descriptions of the pins are listed in tab l e 3 - 1 . 3.1 input voltage supply (v in ) connect the unregulated or regulated input voltage source to v in . if the input voltage source is located several inches away from the ldo or the input source is a battery, it is recommended that an input capacitor be used. a typical input capacitance value of 1 f to 10 f should be sufficient for most applications. 3.2 shutdown control input (shdn ) the shdn input is used to turn the ldo output voltage on and off. when the shdn input is at a logic-high level, the ldo output voltage is enabled. when the shdn input is pulled to a logic-low level, the ldo output voltage is disabled. when the shdn input is pulled low, the pwrgd output also goes low and the ldo enters a low quiescent current shutdown state where the typical quiescent current is 0.1 a. 3.3 ground (gnd) connect the gnd pin of the ldo to a quiet circuit ground. this will help the ldo power supply rejection ratio and noise performance. the ground pin of the ldo only conducts the quiescent current of the ldo (typically 140 a), so a heavy trace is not required. 3.4 power good output (pwrgd) the pwrgd output is an open-drain output used to indicate when the ldo output voltage is within 92% (typically) of its nominal regulation value. the pwrgd output has a typical hysteresis value of 2% for the adjustable voltage version and for voltage outputs less than 2.5v. for fixed output voltage versions greater than 2.5v, the hysteresis is 0.7%. the pwrgd output is delayed on power-up by 200 s (typical, no capacitance on the c delay pin). this delay time is controlled by the c delay pin. 3.5 power good delay set-point input (c delay ) the c delay input sets the power-up delay time for the pwrgd output. by connecting an external capacitor from the c delay pin to ground, the delay times for the pwrgd output can be adjusted from 200 s (no capacitance) to 300 ms (0.1 f capacitor). this allows for the optimal setting of the system reset time. 3.6 output voltage sense input (adj) the output voltage adjust pin (adj) for the adjustable output voltage version of the mcp1726 allows the user to set the output voltage of the ldo by using two external resistors. the adjust pin voltage is 0.41v (typical). 3.7 regulated output voltage (v out ) the v out pin(s) is the regulated output voltage of the ldo. a minimum output capacitance of 1.0 f is required for ldo stability. the mcp1726 is stable with ceramic, tantalum and aluminum-electrolytic capacitors. see section 4.3 ?output capacitor? for output capacitor selection guidance. 3.8 exposed pad (ep) the 3x3 dfn package has an exposed pad on the bottom of the package. this pad should be soldered to the printed circuit board (pcb) to aid in the removal of heat from the package during operation. the exposed pad is at the ground potential of the ldo. table 3-1: pin function table fixed output adjustable output name description 3x3 dfn soic 3x3 dfn soic 1111v in input voltage supply 2222v in input voltage supply 3333shdn shutdown control input (active-low) 4444gndground 5 5 5 5 pwrgd power good output 6666c delay power good delay set-point input ? ? 7 7 adj output voltage sense input (adjustable version) 77??v out regulated output voltage 8888v out regulated output voltage 9 ? 9 ? ep exposed pad
mcp1726 ds20001936d-page 14 ? 2005-2014 microchip technology inc. 4.0 device overview the mcp1726 is a high output current, low dropout (ldo) voltage regulator with an adjustable delay power-good output and shutdown control input. the low dropout voltage of 220 mv at 1a of current makes it ideal for battery-powered applications. unlike other high output current ldos, the mcp1726 only draws 220 a of quiescent current at full load. 4.1 ldo output voltage the mcp1726 ldo is available with either a fixed output voltage or an adjustable output voltage. the allowable output voltage range is 0.8v to 5.5v for both versions. 4.1.1 adjustable input the adjustable version of the mcp1726 uses the adj pin (pin 7) to get the output voltage feedback for output voltage regulation. this allows the user to set the output voltage of the device with two external resistors. the nominal voltage for adj is 0.41v. figure 4-1 shows the adjustable version of the mcp1726. resistors r 1 and r 2 form the resistor divider network necessary to set the output voltage. with this configuration, the equation for setting v out is: equation 4-1: figure 4-1: typical adjustable output voltage application circuit. the range of allowable resistance values for resistor r 2 is 10 k ? to 200 k ? . solving the equation for r 1 yields the following equation: equation 4-2: 4.2 output current and current limiting the mcp1726 ldo is tested and ensured to supply a minimum of 1a of output current. the mcp1726 has no minimum output load, so the output load current can go to 0 ma and the ldo will continue to regulate the output voltage to within tolerance. the mcp1726 also incorporates an output current limit. if the output voltage falls below 0.7v due to an overload condition (usually represents a shorted load condition), the output current is limited to 1.7a (typical). if the overload condition is a soft overload, the mcp1726 will supply higher load currents of up to 3a. the mcp1726 should not be operated in this condition continuously as it may result in failure of the device. however, this does allow for device usage in applications that have higher pulsed load currents having an average output current value of 1a or less. output overload conditions may also result in an overtemperature shutdown of the device. if the junction temperature rises above 150c, the ldo will shut down the output voltage. see section 4.9 ?overtemperature protection? for more information on overtemperature shutdown. 4.3 output capacitor the mcp1726 requires a minimum output capacitance of 1 f for output voltage stability. ceramic capacitors are recommended because of their size, cost and environmental robustness qualities. aluminum-electrolytic and tantalum capacitors can be used on the ldo output as well. the equivalent series resistance (esr) of the electrolytic output capacitor must be no greater than 2 ? . the output capacitor should be located as close to the ldo output as is practical. ceramic materials x7r and x5r have low temperature coefficients and are well within the acceptable esr range required. a typical 1 f x7r 0805 capacitor has an esr of 50 m ? . larger ldo output capacitors can be used with the mcp1726 to improve dynamic performance and power supply ripple rejection performance. a maximum of 22 f is recommended. aluminum-electrolytic capacitors are not recommended for low-temperature applications of < -25c. v out v adj r 1 r 2 + r 2 ------------------- ?? ?? = v out = ldo output voltage v adj = adj pin voltage (typically 0.41v) v in shdn gnd pwrgd c delay adj v out 1 2 3 45 6 7 8 1f v out 4.7 f v in on off v in r 1 r 2 c 1 c 2 1000 pf c 3 mcp1726-adj r 1 r 2 v out v adj ? v adj -------------------------------- ?? ?? = v out = ldo output voltage v adj = adj pin voltage (typically 0.41v)
? 2005-2014 microchip technology inc. ds20001936d-page 15 mcp1726 4.4 input capacitor low input source impedance is necessary for the ldo output to operate properly. when operating from batteries or in applications with long lead length (> 10 inches) between the input source and the ldo, some input capacitance is recommended. a minimum of 1.0 f to 4.7 f is recommended for most applications. for applications that have output step load requirements, the input capacitance of the ldo is very important. the input capacitance provides the ldo with a good local low-impedance source to pull the transient currents from in order to respond quickly to the output load step. for good step response performance, the input capacitor should be of equivalent (or higher) value than the output capacitor. the capacitor should be placed as close to the input of the ldo as is practical. larger input capacitors will also help reduce any high-frequency noise on the input and output of the ldo and reduce the effects of any inductance that exists between the input source voltage and the input capacitance of the ldo. 4.5 power good output (pwrgd) the pwrgd output is used to indicate when the output voltage of the ldo is within 92% (typical value, see the dc characteristics table for min/max specs) of its nominal regulation value. as the output voltage of the ldo rises, the pwrgd output will be held low until the output voltage has exceeded the power good threshold plus the hysteresis value. once this threshold has been exceeded, the power good time delay is started (shown as t pg in the dc characteristics table). the power good time delay is adjustable via the c delay pin of the ldo (see section 4.6 ?c delay input? ). by placing a capacitor from the c delay pin to ground, the power good time delay can be adjusted from 200 s (no capacitance) to 300 ms (0.1 f capacitor). after the time delay period, the pwrgd output will go high, indicating that the output voltage is stable and within regulation limits. if the output voltage of the ldo falls below the power good threshold, the power good output will transition low. the power good circuitry has a 170 s delay when detecting a falling output voltage, which helps to increase noise immunity of the power good output and avoid false triggering of the power good output during fast output transients. see figure 4-2 for power good timing characteristics. when the ldo is put into shutdown mode using the shdn input, the power good output is pulled low immediately, indicating that the output voltage will be out of regulation. the timing diagram for the power good output when using the shutdown input is shown in figure 4-3 . the power good output is an open-drain output that can be pulled up to any voltage that is equal to or less than the ldo input voltage. this output is capable of sinking 1.2 ma (v pwrgd < 0.4v maximum). figure 4-2: power good timing. figure 4-3: power good timing from shutdown. 4.6 c delay input the c delay input is used to provide the power-up delay timing for the power good output, as discussed in the previous section. by adding a capacitor from the c delay pin to ground, the pwrgd power-up time delay can be adjusted from 200 s (no capacitance on c delay ) to 300 ms (0.1 f of capacitance on c delay ). see the dc characteristics table for c delay timing tolerances. t pg t vdet_pwrgd v pwrgd_th v out pwrgd v ol v oh v in shdn v out 30 ms 70 ms t or pwrgd t pg
mcp1726 ds20001936d-page 16 ? 2005-2014 microchip technology inc. once the power good threshold (rising) has been reached, the c delay pin charges the external capacitor to 1.5v (typical; this level can vary between 1.4v and 1.75v across the input voltage range of the part). the pwrgd output will transition high when the c delay pin voltage has charged to 0.42v. if the output falls below the power good threshold limit during the charging time between 0.0v and 0.42v on the c delay pin, the c delay pin voltage will be pulled to ground, thus resetting the timer. the c delay pin will be held low until the output voltage of the ldo has once again risen above the power good rising threshold. a timing diagram showing c delay , pwrgd and v out is shown in figure 4-4 . figure 4-4: c delay and pwrgd timing diagram. 4.7 shutdown input (shdn ) the shdn input is an active-low input signal that turns the ldo on and off. the shdn threshold is a percentage of the input voltage. the typical value of this shutdown threshold is 30% of v in , with minimum and maximum limits over the entire operating temperature range of 45% and 15%, respectively. the shdn input will ignore low-going pulses (pulses meant to shut down the ldo) that are up to 400 ns in pulse width. if the shutdown input is pulled low for more than 400 ns, the ldo will enter shutdown mode. this small bit of filtering helps reject any system noise spikes on the shutdown input signal. on the rising edge of the shdn input, the shutdown circuitry has a 30 s delay before allowing the ldo output to turn on. this delay helps to reject any false turn-on signals or noise on the shdn input signal. after the 30 s delay, the ldo output enters its soft-start period as it rises from 0v to its final regulation value. if the shdn input signal is pulled low during the 30 s delay period, the timer will be reset and the delay time will start over again on the next rising edge of the shdn input. the total time from the shdn input going high (turn-on) to the ldo output being in regulation is typically 100 s. see figure 4-5 for a timing diagram of the shdn input. figure 4-5: shutdown input timing diagram. 4.8 dropout voltage and undervoltage lockout dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below the nominal value that was measured with a v r + 0.5v differential applied. the mcp1726 ldo has a very low dropout voltage specification of 220 mv (typical) at 1a of output current. see the dc characteristics table for maximum dropout voltage specifications. the mcp1726 ldo operates across an input voltage range of 2.3v to 6.0v and incorporates input undervoltage lockout (uvlo) circuitry that keeps the ldo output voltage off until the input voltage reaches a minimum of 2.18v (typical) on the rising edge of the input voltage. as the input voltage falls, the ldo output will remain on until the input voltage level reaches 2.04v (typical). since the mcp1726 ldo undervoltage lockout activates at 2.04v as the input voltage is falling, the dropout voltage specification does not apply for output voltages that are less than 1.9v. for high-current applications, voltage drops across the pcb traces must be taken into account. the trace resistances can cause significant voltage drops between the input voltage source and the ldo. for applications with input voltages near 2.3v, these pcb trace voltage drops can sometimes lower the input voltage enough to trigger a shutdown due to undervoltage lockout. v out t pg v pwrgd_th c delay c delay threshold (0.42v) pwrgd 0v 1.5v (typical) shdn v out 30 s 70 s t or 400 ns (typical)
? 2005-2014 microchip technology inc. ds20001936d-page 17 mcp1726 4.9 overtemperature protection the mcp1726 ldo has temperature-sensing circuitry to prevent the junction temperature from exceeding approximately 150 c. if the ldo junction temperature does reach 150 c, the ldo output will be turned off until the junction temperature cools to approximately 140 c, at which point the ldo output will automatically resume normal operation. if the internal power dissipation continues to be excessive, the device will shut off again. the junction temperature of the die is a function of power dissipation, ambient temperature and package thermal resistance. see section 5.0 ?application circuits/issues? for more information on ldo power dissipation and junction temperature.
mcp1726 ds20001936d-page 18 ? 2005-2014 microchip technology inc. 5.0 application circuits/ issues 5.1 typical application the mcp1726 is used for applications that require high ldo output current and a power good output. figure 5-1: typical application circuit. 5.1.1 application conditions 5.2 power calculations 5.2.1 power dissipation the internal power dissipation within the mcp1726 is a function of input voltage, output voltage, output current and quiescent current. the following equation can be used to calculate the internal power dissipation for the ldo. equation 5-1: in addition to the ldo pass element power dissipation, there is power dissipation within the mcp1726 as a result of quiescent or ground current. the power dissipation as a result of the ground current can be calculated using the following equation: equation 5-2: the total power dissipated within the mcp1726 is the sum of the power dissipated in the ldo pass device and the p i(gnd) term. because of the cmos construction, the typical i gnd for the mcp1726 is 140 a. operating at a maximum of 3.63v results in a power dissipation of 0.51 mw. for most applications, this is small compared to the ldo pass device power dissipation and can be neglected. the maximum continuous operating junction temperature specified for the mcp1726 is +125 c . to estimate the internal junction temperature of the mcp1726, the total internal power dissipation is multiplied by the thermal resistance from junction to ambient (r ? ja ) of the device. the thermal resistance from junction to ambient for the 3x3 dfn package is estimated at 64 c/w. equation 5-3: package type = 8-lead 3x3 dfn input voltage range = 3.3v 10% v in maximum = 3.63v v in minimum = 2.97v v out typical = 2.5v i out =1.0a maximum 1 2 3 4 5 6 7 8 10 f v out =2.5v @ 1a 10 f v in =3.3v on off r 1 c 1 c 2 1000 pf c 3 mcp1726-2.5 10 k ? pwrgd v in shdn gnd pwrgd c delay v out v out v in p ldo v in max ? ?? v out min ?? ? ?? i out max ? ?? ? = p ldo = ldo pass device internal power dissipation v in(max) = maximum input voltage v out(min) = ldo minimum output voltage p ignd ?? v in max ?? i vin ? = p i(gnd) = power dissipation due to the quiescent current of the ldo v in(max) = maximum input voltage i vin = current flowing in the v in pin with no ldo output current (ldo quiescent current) t jmax ?? p total r ? ja ? t amax ?? + = t j(max) = maximum continuous junction temperature p total = total device power dissipation r ? ja = thermal resistance from junction-to-ambient t a(max) = maximum ambient temperature
? 2005-2014 microchip technology inc. ds20001936d-page 19 mcp1726 the maximum power dissipation capability for a package can be calculated given the junction-to-ambient thermal resistance and the maximum ambient temperature for the application. the following equation can be used to determine the package maximum internal power dissipation. equation 5-4: equation 5-5: equation 5-6: 5.3 typical application internal power dissipation, junction temperature rise, junction temperature and maximum power dissipation are calculated in the following example. the power dissipation as a result of ground current is small enough to be neglected. 5.3.1 power dissipation example device junction temperature rise the internal junction temperature rise is a function of internal power dissipation and the thermal resistance from junction to ambient for the application. the thermal resistance from junction to ambient (r ? ja ) is derived from an eia/jedec standard for measuring thermal resistance for small surface-mount packages. the eia/jedec specification is jesd51-7 ?high effective thermal conductivity test board for leaded surface-mount packages?. the standard describes the test method and board specifications for measuring the thermal resistance from junction to ambient. the actual thermal resistance for a particular application can vary depending on many factors, such as copper area and thickness. refer to an792, ?a method to determine how much power a sot23 can dissipate in an application? (ds00792), for more information regarding this subject. p dmax ?? t jmax ?? t amax ?? ? ?? r ? ja --------------------------------------------------- = p d(max) = maximum device power dissipation t j(max) = maximum continuous junction temperature t a(max) = maximum ambient temperature r ? ja = thermal resistance from junction-to-ambient t jrise ?? p dmax ?? r ? ja ? = t j(rise) = rise in device junction temperature over the ambient temperature p d(max) = maximum device power dissipation r ? ja = thermal resistance from junction-to-ambient t j t jrise ?? t a + = t j = junction temperature t j(rise) = rise in device junction temperature over the ambient temperature t a = ambient temperature package package type = 3x3 dfn input voltage v in = 3.3v 10% ldo output voltage and current v out =2.5v i out =1.0a maximum ambient temperature t a(max) =70c internal power dissipation p ldo(max) =[v in(max) ?v out(min) ]xi out(max) p ldo = [(3.3v x 1.1) ? (0.975 x 2.5v)] x1.0a p ldo = 1.192w t j(rise) =p total xr ? ja t j(rise) = 1.192w x 64.0 c/w t j(rise) = 76.3 c
mcp1726 ds20001936d-page 20 ? 2005-2014 microchip technology inc. junction temperature estimate to estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. for this example, the worst-case junction temperature is estimated below. as can be seen from the result, this application will be operating above the maximum operating junction temperature of 125c. the pcb layout for this application is very important, as it has a significant impact on the junction-to-ambient thermal resistance (r ? ja ) of the 3x3 dfn package, which is very important in this application. maximum package power dissipation at 70c ambient temperature from this table you can see the difference in maximum allowable power dissipation between the 3x3 dfn package and the 8-pin soic package. this difference is due to the exposed metal tab on the bottom of the dfn package. the exposed tab of the dfn package provides a very good thermal path from the die of the ldo to the pcb. the pcb then acts like a heat sink, providing more area to distribute the heat generated by the ldo. when the pcb heat sink area is used, the r ? ja should be replaced by r ? jc plus r ? hs , where r ? hs is the pcb copper area heat sink thermal resistance. this will allow for higher maximum power dissipation compared to the free-air power dissipation calculated using r ? ja . t j =t jrise +t a(max) t j = 76.3c + 70.0c t j = 146.3c 3x3 dfn (64c/w r ? ja ) p d(max) = (125c ? 70c)/64c/w p d(max) =0.86w 8ld soic (163c/w r ? ja ) p d(max) = (125c ? 70c)/163c/w p d(max) = 0.337w
? 2005-2014 microchip technology inc. ds20001936d-page 21 mcp1726 6.0 packaging information 6.1 package marking information nnn 8-lead dfn (3x3x0.9 mm) example legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e voltage option code 0.8v caaa 1.2v caab 1.8v caac 2.5v caad 3.0v caae 3.3v caaf 5.0v caag adj aadj caaa e438 256 8-lead soic (3.90 mm) example 1726adje sn ^^1438 256 3 e
mcp1726 ds20001936d-page 22 ? 2005-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2005-2014 microchip technology inc. ds20001936d-page 23 mcp1726 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp1726 ds20001936d-page 24 ? 2005-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2005-2014 microchip technology inc. ds20001936d-page 25 mcp1726 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp1726 ds20001936d-page 26 2005-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2005-2014 microchip technology inc. ds20001936d-page 23 mcp1726 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp1726 ds20001936d-page 28 ? 2005-2014 microchip technology inc. notes:
? 2005-2014 microchip technology inc. ds20001936d-page 29 mcp1726 appendix a: revision history revision d (september 2014) the following is the list of modifications: 1. corrected the typical output voltage tolerance in the features section to match the stated value in the dc characteristics table. 2. corrected illustrations of package markings in section 6.0, packaging information . 3. minor typographical changes. revision c (august 2007) the following is the list of modifications: 1. added 3.0v option to section 6.1, package marking information . 2. updated package outline drawings. 3. added 3.0v option to product identification system (pis) section. revision b (march 2005) the following is the list of modifications: 1. replaced 3x3 dfn package diagram. 2. emphasized (bolded) a few specifications of section 1.0, electrical characteristics in the dc characteristics table. revision a (february 2005) ? original release of this document.
mcp1726 ds20001936d-page 30 ? 2005-2014 microchip technology inc. product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp1726: 1a, low quiescent current ldo regulator tape & reel option: t = tape and reel blank = tube standard output voltage*: 080 = 0.80v 120 = 1.20v 180 = 1.80v 250 = 2.50v 300 = 3.00v 330 = 3.30v 500 = 5.00v adj = adjustable voltage version * custom output voltages available upon request. contact your local microchip sales offi ce for more information. tolerance: 2 = 2.0% temperature range: e=-40 ? to +125 ? c package*: sn = plastic small outline ? narrow, 3.90 mm body, 8-lead (soic) mf = plastic dual flat, no lead package ? 3x3x0.9 mm body, 8-lead (dfn) *both packages are lead free part no. x xx package temperature device examples: a) mcp1726-0802e/mf: 0.80v, 1a ldo, 8ld dfn package b) mcp1726t-1202e/mf: tape and reel, 1.20v, 1a ldo, 8ld dfn package c) mcp1726-3002e/mf: 3.00v, 1a ldo, 8ld dfn package d) mcp1726t-3302e/mf: tape and reel, 3.30v, 1a ldo, 8ld dfn package e) mcp1726-1802e/sn: 1.80v, 1a ldo, 8ld soic package f) mcp1726t-2502e/sn: tape and reel, 2.50v, 1a ldo, 8ld soic package g) mcp1726-5002e/sn: 5.00v, 1a ldo, 8ld soic package h) mcp1726t-adje/sn: tape and reel, adjustable, 1a ldo, 8ld soic package range x tolerance -xxx voltage output x tape & reel note 1: tape and reel identifier only appears in the catalog part number description. this identi- fier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option.
? 2005-2014 microchip technology inc. ds20001936d-page 31 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2005-2014, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-63276-576-5 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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